Integrated circuits may be housed in a plurality of chip packages. A Multi-Chip Module (MCM) is a chip package that contains two or more dies mounted close together on a substrate base. The short traces between the chips can increase performance relative to individually packaged chips, such as by reducing noise that external traces between individual chip packages can produce, thereby allowing higher frequency of operation, and by allowing CMOS and bipolar technologies to be used in the same package. A form of MCM is a System-In-Package (SIP), which includes a single package, housing a multi-die semiconductor system. The terms “MCM” and “SIP” are used here interchangeably throughout. A SIP with multiple dies can replace part or all of a printed circuit board (PCB), and can include a variety of chip packages.
Integrated circuit chips are tested during various stages of manufacture with production tests. One such test is a final test on a packaged die. In a scan-design test, the chip or die, which has been designed in accordance with so-called design for test (DFT) techniques or principles prior to manufacture, has test data inputs applied to the die placed under test mode, and outputs are observed and compared to predicted results. Registers (flip-flops) in the design are connected in one or more scan chains, which are used to gain access to internal nodes of the chip. Test patterns are shifted into the chip(s) via the scan chain(s) during a serial phase, followed by a parallel phase where the clock signal is pulsed one or more times to test the circuit. The results of the test are captured in the flip-flops and are then shifted out to the die output pins and compared against predicted results. Variance between actual output and predicted output indicates a failure.
Scan chains are thus used in chips designed for test. In scan chain enabled chips, a special signal called scan enable is added to the chip. When a scan enable signal is asserted, every flip-flop in the scan chain is effectively connected into a long shift register, with one input pin providing the data to the scan chain, and one output pin providing the output of the scan chain. A specific data pattern may be entered into the chain of flip-flops. The data pattern sets the internal state of the chip into a desired state to test certain features. The clock is pulsed one or more times to exercise the chip, and the state of every flip-flop may be read to observe the outcome of the test by shifting out the scan chain. In a full scan design, all flip-flops are included in a scan chain. Other variants include a partial scan, where only some of the flip-flops are connected into a chain; multiple scan chains, where two or more scan chains are built in parallel, to reduce the time to load and observe test data; and test compression, where the input to the scan chain is driven by on-board logic that decompresses the input received. Further, various test algorithms may be used to efficiently test a large IC in a given fixed period of time using test vectors, and often using specialized equipment and design tools, such as automatic test-pattern generation (ATPG) and automatic test-vector generation (ATVG) electronic design automation tools. In addition, chips that are designed for test may be designed with Built-In Self Test (BIST) logic, to obviate the need for external test signals. However, the results of such BIST tests have to be accessed, controlled and observed through external pins.
Referring now to FIG. 1, there is shown a representative scan chain 100 of the kind used in a chip internal scan test. A plurality of clocked flip-flops 112, 114, shown as D-type flip-flops, are linked together in a daisy chain fashion inside a chip to form a serial shift register 100, called a scan chain. A plurality of these scan chains may exist within a chip.
As shown in FIG. 1, the input to each flip-flop is multiplexed, so that the D input is chosen from either the scan chain output from the previous flip-flop or the normal input. First D-type flip-flop 112 receives a signal from either normal input 116 or the output 118 from the previous flip-flop, D-type flip-flop 114 daisy chained in series, and acting through mux 120. Similarly, D-type flip-flop 114 receives a signal controlled by mux 121 from either its normal input 122 or the output 124 from a previous flip-flop (not shown) that forms part of the serial shift register scan chain 100. Output 126 from the D-type flip-flop 112 may likewise be connected in a daisy chain fashion to another flip-flop (not shown) in the same manner flip-flop 114 is connected to flip-flop 112. D flip-flops 112, 114 may be synchronous (or clocked) flip-flops, each having a clock signal line CLK as shown.
When flip-flops 112, 114 are connected in the manner shown in FIG. 1, the scan chain is called a muxed scan. Operation of the muxed scan is as follows. Predetermined patterns are shifted through the scan chains. These patterns can be of any number of patterns, such as, by way of illustration and not limitation, stuck at fault models; test vectors of any kind, such as pseudorandom test vectors, generated by pseudorandom test generation or any other kind of test pattern.
When performing scan testing of an IC die through the scan chain methodology as illustrated in FIG. 1, the IC is placed into a test mode through control signals, whereby several of the pad inputs to the IC become inputs to scan chains, such as scan chain 100, and several of the pad outputs of the IC become scan outputs. Additionally, the muxes 120, 121 can be controlled so that they either allow input data to pass normally to the D flip-flops 112, 114, or to shift out data serially so the D flip-flops receive data from their neighboring flip-flops, in a daisy chain fashion. Once placed into test mode, the muxes are set to select the data from the prior flip-flop of the scan chain. The scan chains are loaded with a test pattern by applying the test pattern serially to the pad inputs while strobing the CLK signal. Once the test patterns are loaded into the scan chains, the muxes are set to select the normal input. The CLK signal is strobed one or more times to propagate the signals from the flip-flops, through the combinatorial logic of the chip, into the inputs of flip-flops that are on scan chain. The muxes are then set to once again connect the scan chain.
Upon the application of a suitable number of control signals and clock pulses, the scan chains are scanned out at their normal Q output (e.g., outputs 118, 126 of D flip-flops 112, 114), and the data shifted out of each flip-flop is compared to expected data. A variance between expected data and received output data indicates the presence of manufacturing faults within the IC. For example, no signal received in one flip-flop from a neighboring flip-flop might indicate an open circuit somewhere in the interconnect in-between the two flip-flops.
A tenet in IC testing is controllability and observability through the use of external pins on a chip. Test controllability refers to the ability to apply a desired test stimulus at the input of the die. Test controllability also refers to activating or deactivating logic blocks internal to the IC for testing, such as through a scan enable signal, or activating a BIST. Test observability refers to the ability to observe and evaluate the results of the IC test. For scan testing, test observability means that the output of the scan chains can be observed. It should be understood that testing of an IC may include other kinds of tests than the above tests, as is known in the art.
In all tests of a complex IC, a reoccurring problem is the number of pins needed to execute the tests. Two factors exacerbate the problem of sufficient pins for scan-testing complex ICs. First, since complex ICs have many cells, megacells and embedded blocks of logic, a large number of logic elements must be tested. It is desirable to have a large number of scan chains to reduce the test time. However, a relatively large number of scan chains generally requires a large number of pins. Secondly, as ICs encompass whole electronic systems, the number of functional pins may actually decrease, as most of the interconnects previously found between ICs are absorbed into the single complex IC.
Scan testing multiple dies in a package such as a SIP can create problems, such as creating hidden scan chains that are not externally controllable or observable. Many input/output (I/O) signals of the dies in a SIP package are no longer available once these dies are incorporated into the SIP package. Instead, the dies are connected to their destination within the SIP itself using internal pins, hidden from external view and without being exposed to external access and control through SIP package external pins. These internal hidden connections no longer provide a means of functioning as the scan-in head or scan-out tail of the scan chains, such as scan chain 100 in FIG. 1. Further, once the dies are assembled in the SIP package, there is no easy, non-destructive way of testing the SIP package dies individually without using separate I/O pins for each device.
The above problems may be solved by less advantageous solutions than proposed by the present invention. For example, some or all dies in a SIP package may be redesigned to have fewer scan chains, and/or the scan chains may be relocated to signals which are connected to pins in the SIP package so that they can receive and transmit external signals. In other words, in the latter solution, if internal scan chains are present that are hidden from external view, one may make these hidden scan chains less hidden and accessible to external view by moving them to external pins. Another less advantageous alternative solution to the present invention would be to increase the pin count of the SIP package to provide access to all scan chains. However, it may not be practical or possible to increase the pin count. In any case, these less advantageous solutions add cost to the SIP package and/or are relatively time consuming; for example, it can take months to redesign dies and/or the SIP package in this way.
Therefore, it is desirable to provide a method and device for scan chain management of dies in a SIP or MCM package that overcomes problems relating to scan chain testing of existing dies in a SIP package, as well as to provide other advantages as disclosed in the specification and claims herein.